Jedec
英
美
网络 电子器件工程联合委员会; 固态技术协会; 电子器件工程联合会; 电子元件工业联合会; 电子工程设计发展联合协会
双语例句
- Some data sheets contain electrostatic discharge or latch-up TEST results and the associated JEDEC TEST conditions.
有的数据手册还包括静电或闩锁测试结果以及对应的JEDEC测试条件。 - JEDEC? The voltage level at an output terminal with input conditions applied that, according to the product specification, will establish a high level at the output.
根据产品技术规范，随加到输入端的情况在输出端的电平，将在输出端建立一个高电平。 - JEDEC? The current into an input terminal when a specified high-level voltage is applied to that input.
一个规定的高电平电压信号加到一个输入端时，流进该输入端的电流。 - Samsung now plans to work closely with a number of server makers to help insure completion of JEDEC standardization of DDR4 technologies in the second half of this year.
三星目前正计划与多家服务器厂商合作，以尽快在今年下半年完成DDR4JEDEC标准的制定工作。 - The two companies started participating in standardization efforts for DDR2.0 through the JEDEC Solid State Technology Association, last month.
上个月，两家公司便已经参与到了由JEDEC固态技术协会牵头的DDR2.0NAND接口标准化工作中去。 - JEDEC – A power supply that acts as a reference for determining internal threshold voltages, but does not supply any substantial power to the device.
为确定内部门限电压而提供参考的电源，但它并非为器件提供实际的电源（电力）。 - JEDEC? The input threshold voltage when the input voltage is falling.
在输入电压下降时的输入门限电压。 - A Case Study of Problems in EIA/ JEDEC HBM ESD Test Standard
静电放电人体模型测试标准EIA/JEDEC中的问题研究 - After the system start, MTD will identify flash chip supporting CFI or JEDEC interface. And it can read CFI query structure by querying command.
MTD在系统启动后自动识别支持CFI或JEDEC接口的FLASH芯片，之后通过查询命令读取CFI查询结构。 - Leaded and lead-free BGA ( ball grid array) components were tested in board level drop test defined in the JEDEC ( Joint Electron Device Engineering Council) standard.
按照JEDEC标准对板级跌落实验的要求测试了有铅和无铅焊点的球栅阵列封装。 - Secondly, the using of JEDEC Standard SDP three-byte command sequence can reduce the accessing EEPROM by accident and improve the dependability of saving data.
其次SST29EE020采用JEDECStandardSDP三字节命令时序减少了对EEPROM的误操作，提高了数据保存的可靠性。 - The chips on board would not damage at the same time in finite drop. Large number of studies show that the chip closed to the JEDEC board bolt location ( U1) is the easiest damage part.
有限次跌落并不使板上的芯片同时失效，很多研究表明在跌落试验板靠近角边螺栓孔位置的芯片最易于破坏。