RTL
英
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网络 寄存器传输级; 寄存器级; 从右到左; 保留时间锁定; 卢森堡广播电视台
双语例句
- RTL is a low-level representation very close to assembly language ( inspired by LISP S-expressions).
RTL是非常接近于汇编语言的一种低级的表示（受LISPS表达式的影响）。 - The optimized RTL is then fed to the code generator, which produces target code.
然后，优化后的RTL被提供给代码生成器，后者产生目标代码。 - The front end of a compiler is language specific and includes a parser for the given language that results in parsed trees and the intermediate representation ( the Register Transfer Language, or RTL).
编译器的前端是特定于语言的，它包括一个用于给定语言的解析器，这个解析器产生经过解析的树和中间表示（RegisterTransferLanguage，RTL）。 - To do this, the optimizer uses the RTL to create fast or more compact code ( or both, when possible).
为此，优化器使用RTL创建快速的或紧凑的代码（或者两者兼顾）。 - Finally, the SSA trees are converted into RTL, which the back end uses for target code generation.
最后，SSA树被转换成RTL，后者被后端用于目标生成代码。 - Optimizations that require higher-level information about the program may not be possible, because their expression is lost in RTL.
需要关于程序的高级信息的优化可能无法实现，因为无法用RTL表达它们。 - The problem with RTL is that the optimizations it enables are those close to the target.
RTL的问题是，它支持的优化是接近于目标的。 - The Syrian government has enough money to hold out for only a few months without the support of Russia and Iran as the civil conflict costs it about 1 billion ($ 1.23 billion) a month, Mr. Fabius said in an interview with French radio station RTL.
法比尤斯对法国广播电台RTL说，叙利亚政府用于内战的花费大概为每月10亿欧元（约合12.3亿美元），因此在没有俄罗斯或伊朗支持的情况下，叙利亚政府的资金只能再维持几个月的时间。 - Her gynaecologist, Kai Hertwig, was quoted on the RTL website ahead of Monday's broadcast as saying that quadruple pregnancies were always a strain but that everything was currently going well.
在13日访谈播出前，RTL网站引用她的妇科医生卡伊·赫特维希的话称：怀有四胞胎难免要承受压力，但目前一切都进行得很顺利。 - The RTL design and FPGA implementation of OPB arbiter device
OPB总线仲裁器的RTL设计与FPGA实现 - Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level ( RTL) is a promising solution.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。 - "One thing's for sure: we're not selling him to Manchester United," Wenger told the French radio station RTL.
“一个是确定的，我们不会把他卖给曼联，”温格告诉法国电台RTL。 - If the document's dir property is set to rtl, the selection glyph is on the right.
如果文档的dir属性设置为rtl，则选择标志符号在右边。 - Anna-Bell told the German television station RTL: "We wanted to get married and so we just thought:'Let's go there."
安娜·贝尔告诉德国RTL电视台说：“我们想结婚，于是我们就想‘我们去非洲吧。’” - The European group, which said in March that it was looking to secure a deal with a local partner in India, said the two had agreed to form a new joint venture company that would initially produce two English language channels.
今年3月曾表示正在寻求与印度本土合作伙伴达成协议的RTL表示，两家公司已同意成立一家新的合资公司，初期将推出两个英语频道。 - FPGA-Based Approach for RT Level Circuit Power Estimation
一种基于FPGA的RTL级电路功耗评估方法 - Equivalence Checking between System Level Model and RTL Implementation
系统级模型与RTL实现的等价性验证方法 - We base on it to establish abstract model between the sequential executable codes and the register transfer level ( RTL) description.
我们依该方法在循序可执行程式码和暂存器传输层级间建立抽象模型。 - "Application of the Transistor Charge Control Model to Predict RTL and DTL Transient Response"
应用晶体管电荷控制模型预示电阻-晶体管逻辑和二极管-三极管逻辑电路的瞬态响应 - Hahn, who lives on200 euros a week and has his rent paid by his mother, said he wanted to use some of the rest of the cash to finance his studies and buy a rail pass, RTL said.
目前，哈恩每周的生活费为200欧元，房租一直靠母亲资助。他表示，在父母办完婚事后，他将用剩下的钱去读书并为自己买一张德国的火车通票。 - Research on how to use tool to do RTL synthesis
怎样能更好地应用工具进行RTL综合研究 - Xinghe Farming Instruments Supermarket Management Company and its multiple shops in whole China are all under the management of RTL, also with China Farming Instruments Net as a branch.
公司旗下有“兴和畜牧器械超市经营管理公司及其全国各地连锁店”、“中国畜牧设备器械网”。 - An alternative way to solve this is to formally prove that the RTL code and the netlist synthesized from it have exactly the same behavior in all cases.
另一种方式来解决，这是正式证明，RTL代码和网表合成具有完全相同的行为在所有的案件。 - Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。 - The design of Data-RAM on gates level and physical level can be directed by this RTL module.
Data-RAM的RTL模型设计为门级和物理级的性能设计提供了参考。 - The RTL design of the module is completed using Verilog.
针对该芯片的架构，提出了缓冲器管理单元的设计方案，并应用Verilog语言完成了该单元的RTL级设计。 - The RTL-level design and verification of the three modules using the Verilog hardware description language is completed.
使用Verilog硬件描述语言完成了三个运算逻辑模块RTL级的设计与验证。 - Detailed RTL-level design of this controller is carried out on Altera Quartus ⅱ software with the top-to-down approach.
利用Altera公司的EDA工具QuartusⅡ软件，采用自顶向下的方法对该控制器进行了RTL级详细设计。