latch-up
英 [lætʃ ʌp]
美 [lætʃ ʌp]
网络 闩锁; 闩锁效应; 闭锁; 栓锁效应; 闩锁现象
双语例句
- Problems with high on-resistance that are seen in traditional vertical structure DMOSFET still appear in LDMOSFET and phenomena of turn-off delay and latch-up are seen in LIGBT as well.
传统垂直式DMOSFET高导通电阻的缺点在LDMOSFET中依旧存在，而垂直式IGBT关闭延迟和闩锁的现象，也在LIGBT中发生。 - Some data sheets contain electrostatic discharge or latch-up TEST results and the associated JEDEC TEST conditions.
有的数据手册还包括静电或闩锁测试结果以及对应的JEDEC测试条件。 - Latch-up Problem Resulting from Negative Undershoot of High-voltage-side Floating Reference in Bootstrap Gate-drive IC
自举高端驱动浮动地负过冲闭锁问题 - Latch-up Free Design of SCR-Based ESD Protection Circuits
基于SCR的ESD保护电路防闩锁设计 - Intelligent Latch-up Anti-drink Driving System Based on PIC Single-chip
基于PIC单片机的酒后驾驶智能闭锁系统设计 - In Power IC, crosstalk between high voltage power devices and low voltage devices can cause circuit operation failure and even latch-up.
在功率集成电路中，高压功率器件会对周围的低压电路产生串扰，从而造成电路失效甚至闭锁等现象。 - The switching action of the comparator and diode D3 prevents latch-up due to a large positive-boost transient.
比较器和二极管D3的切换行动防止由于一个瞬间的正极充电引起的闭锁。 - Based on this, a "three-path" latch-up model is developed to explain the window phenomena.
在此基础上，提出了解释窗口现象的“三径”闭锁模型。 - The parasitic pnpn structure exists inherently in bulk CMOS IC. It leads devices to Latch-up failures under certain conditions.
体硅CMOSIC内不可避免地存在着寄生pnpn四层结构，在一定条件下，导致器件闭锁失效。 - A Novel ESD Clamp Protection Circuit with Low Leakage Current and High Latch-up Immunity
新型低泄漏防闩锁ESD钳位保护电路 - The technology method for IC to overcome single-event upset and single-event latch-up is suggested.
提出提高集成电路抗单粒子翻转和单粒子闭锁的技术路径。 - The three-path latch-up window model is simply based on the analysis of CMOS device latch-up circuit model.
在分析CMOS器件闭锁电路模型的基础上，简要介绍了三径闭锁窗口模型的有关情况。 - To find the cause of latch-up window phenomena many references concerned in detail are studied and the reciprocity of several paths in CMOS devices is analyzed by circuit simulation software on computer.
为了获得闭锁窗口的出现原因，借助对窗口现象的有关参考文献的研究，利用计算机电路模拟软件，分析了CMOS器件多个闭锁路径之间的相互作用。 - Analysis and Computer Simulation of a CMOS Latch-up Model
CMOS闩锁效应模型分析及计算机模拟 - A technology for protection from latch-up based on current rejection by LDO
基于LDO限流技术的辐射闩锁防护技术 - Study on the mechanism of Latch-up effect in CMOS IC and its countermeasures
CMOS集成电路闩锁效应的形成机理和对抗措施研究 - When trying to explain the latch-up window phenomena in CMOS devices induced by radiation, the so called three-path latch-up window model is provided.
在解释CMOS器件辐射感应的闭锁窗口现象时，提出了所谓的三径闭锁窗口模型。 - When CMOS devices are irradiated by transient radiation, phenomena of latch-up single window or multi-window may appear.
中、大规模CMOS器件受到瞬态辐射时，出现了闭锁单窗口、多窗口现象。 - Over-Current Protection Circuit for Improving Regulators 'Latch-up Effect
一种可改善稳压器闩锁效应的过流保护电路 - To verify the model, a test circuit has been designed to simulate parasitical latch-up paths in CMOS devices and relevant parameters are reported.
为了实验验证该模型，设计了实验电路以模拟CMOS器件的寄生闭锁路径，给出了相应的参数。 - Experiment study of three-path latch-up window model
三径闭锁窗口模型的实验研究 - There are two failure modes in the manufacturing system of electronics in common: The ESD static damage and LATCH-UP failure that gives brief introduction about the index and theory of the reliability.
在电子产品制造系统中，常常有两种失效模式：ESD静电损伤和LATCH-UP失效现象，对以上可靠性指标和理论作简要的论述。 - Based on the analysis of two protection methods, an over-current protection circuit which can improve the integrated regulators 'latch-up effect is proposed.
分析了两种过流保护方法的功能及优缺点，研究并提出了一种可应用于集成稳压器中改善闩锁效应的foldback过流保护电路。 - Analysis and Prevention of Latch-up in Closed Polysilicon Gate CMOS ICs
封闭硅栅CMOS电路中锁定的分析与防止 - Study on the Latch-up Effect of CMOS IC by Using Microelectronic Test Patterns
利用微电子测试图形研究CMOSIC的锁定效应 - Numerical Simulation For Parasitic parameters in Bulk CMOS and Test Analysis of Its Latch-up Resistibility
体硅CMOS寄生参数的数值模拟及抗闩锁能力的测试分析 - On the other hand, SOI technology has the advantages of high-speed, latch-up free, low-power, radiation, and miniaturization.
另一方面，SOI技术具有高速、无闩锁、低功耗、抗辐射和小型化等优点。 - At last the paper introduced the principle of latch-up effect, and introduced the method of preventing the latch up separately from the technology and layout design.
论文最后介绍了闩锁效应产生的原理，和闩锁效应的触发方式，并且分别从工艺和版图设计方面研究了防止闩锁产生的方法。 - Secondly, the latest system-level ESD protection were analyzed, According to system-level ESD failure mechanism, a hardware and software co-design solution is proposed, which can effectively solve the system-level ESD failures due to latch-up effect.
接着对最新出现的系统级ESD防护进行了系统分析，根据系统级ESD失效机理，提出了软硬件协同设计的解决方案并有效地解决系统级ESD失效引起的闩锁效应。