off-chip
英 [ɒf tʃɪp]
美 [ɔːf tʃɪp]
网络 片外; 芯片外; 晶片外; 芯片外部; 在芯片外
双语例句
- L3 directory on chip reduces off-chip delays after an L2 miss
芯片上L3目录可以减少发生L2未命中之后的离片延迟 - By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor.
通过采用片上极点分离技术和片上零极点抵消技术，保证了没有片外电容情况下低压差稳压器的稳定性。 - Low dropout linear regulator with no off-chip capacitor and low power consumption
低功耗无片外电容的低压差线性稳压器 - It connects all masters and slaves in the system in a parallel fashion and enables data transfers between peripherals and on-and off-chip memories without any CPU intervention.
它采用并行方式连接系统内的所有主从设备，无需CPU参与即可在外设和片内片外存储器间传输数据。 - This algorithm ensured the average times of off-chip access close to1 through changing the operating sequence and data structure of peacock hash.
该算法从改变表的操作顺序及修改孔雀哈希数据结构着手，保证了片外访问的平均次数接近于1。 - DVS enables the system to run in a lower supply voltage when the system is running at low frequencies by controlling the off-chip converter.
DVS技术更进一步的让系统在低频率运行的同时，控制片外的逆变器使得系统的供电电压也同时降低，进一步降低了系统的功耗。 - In order to reduce the on-chip memory space, if parts of program and data are stored in off-chip memory and are loaded into on-chip memory during execution time, this would increase the I/ O overhead.
为了减少片上存储部件，则部分程序和数据移到片外存储，在执行时轮流调进到芯片内，势必增加I/O的开销。 - In response to the disadvantages of register window method of Berkeley RISC processor, this paper presents an improved archi-tecture with an off-chip special stack memory.
本文通过分析BerkeleyRISC处理器寄存器窗口方法的特点，针对其不足之处提出改进其结构的方法，并给出增加一个芯片外专用堆栈存储器的改进体系结构的设想。 - In Chapter four, this paper focus on several schemes on the implementation of video decoder in the space restricted system, presents their advantages and disadvantages, and the optimization of the off-chip frame storage.
在第四章中，本文重点探讨了空间受限系统中视频解码器实现的几种方案及其各自的优缺点，以及外部帧存储器的优化设计。 - Split read and off-chip cache are used in this scheme to improve the processor performance.
该接口部件通过使用Split读和片外Cache来提高处理器的性能。 - This dissertation mainly focuses on the performance of off-chip memory system. It introduces how to model SDRAM controller in C language, analyzes the impact of open page and bank interleave, and evaluates the effect of page hit and bank interleave by different address mapping manner.
本文主要讨论龙芯2号片外存储系统性能，介绍了SDRAM控制器的建模方法，分析了OpenPage和bankinterleave对系统性能的影响，评价了不同地址映射方式对page命中和bankinterleave的影响。 - Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。 - On-chip active inductor load, off-chip bonding-wire parasitic inductor load, self-biased technology and direct-coupled technology are employed to increase the gain, widen the bandwidth and reduce the power dissipation of the proposed laser diode driver.
电路采用了有源电感负载技术、键合线寄生电感负载技术、自偏置技术和放大级直接耦合技术以提高增益、拓展带宽、降低功耗。 - With the development of microprocessor design techniques, cache memories are widely employed to bridge the increasing performance gap between the processor and the off-chip main memory.
随着微处理器设计技术的不断发展，Cache得到了广泛应用，以解决处理器与主存之间性能差距越来越大的难题。 - A perfect SRF allocation scheme should avoid introducing extra off-chip memory transfers, efficiently capture the widely existed producer-consumer locality, and exploit the parallelism between computation and memory access.
优良的SRF分配方案还应能在避免引入额外的片外存储器传输的前提下，有效地捕获流应用中广泛存在的生产者消费者局部性，并尽可能地开发计算与访存并行。 - When loading a program from the off-chip memory into SRF for execution, the storage consumption and the data transfer time are two key factors which affect the system performance.
因此，将程序由主存载入SRF中执行时，对SRF的空间需求以及数据传输时间成了影响系统性能的两个重要因素。 - The hardware design includes six-way A/ D channels design, off-chip memory expansion and Bluetooth communication circuit design.
硬件设计主要包括前端六路A/D数据采集通道设计、片外存储器扩展设计以及蓝牙通信电路设计。 - Minimizing the off-chip components is becoming one of the targets when doing chip design.
尽可能减少片外元器件的数目也成为芯片设计所追求的目标之一。 - However, the increasing number of processors cores on a single chip increases the demand on two critical resources: the shared L2 cache capacity and the off-chip pin bandwidth.
然而，在单芯片上集成越来越多的处理器内核增加了对两个关键资源的需求：共享二级缓存容量和片外引脚带宽。 - Thanks to the development of modern semiconductor process, more off-chip components are integrated into the chip for minimizing external pins and making it easy to use.
随着现代半导体工艺的不断发展，更多的外围器件实现了片内集成，减少了芯片的引脚数，极大地方便了应用。 - Then, we design and implement a Shared by Heterogeneity Processor L2 Cache sub-system to exploit the extra parallelism and locality in stream application, and improve the off-chip memory bandwidth. These lead to a more completed parallel hierarchy stream memory system.
针对流应用中各种可用的并行性和局域性，我们设计并实现了由异构处理器共享的二级缓存子系统，并对片外存储层次进行改进，完善了原有的存储层次结构。 - Hence, current VCO is often implemented by an external PN junction varactor. The off-chip device not only increases final system area, but also increases package complexity, power consumption and cost.
因此，现在的VCO器件通常采用片外分立的PN结变容二极管，这样不仅增加了系统的面积，而且存在封装复杂、功耗高以及成本高等缺点。 - The LDO without off-chip capacitor can be implemented on chip, so that it would become the mainstream according to the development of SOC.
无片外电容的LDO可实现片上集成，随着SOC的进一步发展，必将越来越成为主流。 - This thesis studies a multicore system model where each core has a private cache and all cores use a shared bus to access the off-chip memory.
本文所研究的多核系统模型是每个处理器核心都拥有一个私有的Cache，并且这些处理器核心可以通过共享访存总线来对主存进行访问。 - In the system, the hardware implementation of the transport stream input, video displaying and audio playing has been resolved. In addition, high-speed data exchange between on-chip and off-chip memory space is implemented successfully with hardware means.
该硬件系统解决了传送流输入、视频显示和音频播放的硬件实现，还通过硬件手段较好地解决了系统高数据吞吐率的问题。 - Different with hardware-managed cache, software-managed on-chip memory relies on software to explicitly manage all the data transfers between on-chip memory and off-chip memory, and decide when and where the data will enter into memory.
与硬件管理的cache不同，软件管理的片上存储器需要由软件通过数据传输语句显式地管理所有片上与片外存储器之间的数据传输，决定数据进入存储器的时机和位置。 - The limited off-chip bandwidth of memory system has become the huge obstacle for boosting the performance of applications.
存储系统有限的片外带宽已经成为阻碍程序整体性能提升的瓶颈。 - This memory system can efficiently reduce the total times of off-chip memory access through hierarchical scheduling, which alleviates the needs of off-chip bandwidth.
该存储系统通过多级调度能有效地减少片外访存的次数，降低片外带宽需求。 - Thirdly, based on the consideration of improving the utilizing efficiency of off-chip bandwidth, we have designed and implemented a data-parallel memory system for our Tiled Stream Processor in current project.
从提高片外带宽使用率的角度出发，设计和实现了分片式流处理器的数据并行存储系统。 - On-chip memory is widely employed in commercial computing devices to reduce the performance gap between processors and off-chip memory.
为了应对这个挑战，现代商业计算设备中广泛地应用了片上存储的方案，以缓解处理器与存储设备之间的性能差距。