sample-and-hold
英 [ˈsɑːmpl ənd həʊld]
美 [ˈsæmpl ənd hoʊld]
网络 取样保持; 采样与保持; 取样与保存; 采样保持; 取样与保持
双语例句
- A sample-and-hold ( S/ H) circuit as the key part of the analog-to-digital ( A/ D) converter always attracts the researcher and designer of A/ D converter.
采样保持电路作为流水线模数转换器中的重要单元一直是高速高分辨率模数转换器研究设计者十分关注的内容。 - It is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference.
这是一款完整的单芯片ADC，内置片内高性能、低噪声采样保持放大器和可编程基准电压源。 - A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.
设计了一个用于流水线型模数转换器的低压采样保持电路。 - Design and Implementation of a High-speed High-resolution Sample-and-hold Circuit
一种高速高精度采样/保持电路的设计与实现 - Study of Sample-and-hold Circuit Based on Pipeline ADC
基于流水线ADC的采样保持电路的研究 - Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges.
每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。 - The analog input is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-and-hold circuitry.
模拟输入由模拟调制器以时钟频率两倍的速度连续采样，因而无需外部采样保持电路。 - The output of the sample-and-hold system now goes into an analog-to-digital converter.
取样和保持系统的输出现在又进入一个模数转换器。 - Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
采样速度和保持精度，是采样保持电路设计制作者最为关注的两项指标。 - Design of a High-Precision Sample-and-Hold Circuit
高精度的采样保持电路的设计 - For this signal, a general phase detector can not be used, sample-and-hold phase detector must be used in the phase-locked loop recovering the standard frequency signal.
对于这种信号，在接收端用锁相环路恢复标准频率时，不能使用普通的鉴相器，必须用采样保持鉴相器。 - A New High-Speed and High-Resolution Sample-and-Hold Circuit
一种新型高速高分辨率采样保持电路 - Based on the sample-and-hold scheme in the classic fractional-N phase-locked loop ( PLL), a novel sample-and-hold scheme was proposed for the wideband Σ-Δ PLL.
根据传统的小数分频锁相环中的采样保持方案，提出了宽带∑-Δ锁相环中采样保持技术的实现方案。 - Analysis and Design of Fully Differential Gain-boosted OPAMP Dedicated to 14 bit Sample-and-Hold Circuit
一个用于14位采样保持电路的全差分增益增强放大器的分析和设计 - Design of a High-Speed Flip-Around Sample-and-Hold Circuit
Flip-around结构高速采样保持电路的设计 - A Study on Filter Circuits Based on Sample-and-Hold Amplifier
基于采样保持器的滤波电路研究 - With this switch, the clock voltage can be boosted from 0-3 V to 0-6 V. The device can find applications in sample-and-hold circuits for A/ D converters and filter circuits based on switched-capacitors.
输入信号通过该开关后，动态范围达到满幅度，并能将0～3V的时钟电压提升到0～6V。该开关适用于A/D转换器中的采样/保持电路和开关电容的滤波电路。 - When sample-and-hold amplifier ( SHA) was set at the input ports, low power dissipation operational trans-conductance amplifier ( OTA) and the dynamic comparators were designed in the sub-stage circuits, and sampling capacitors optimization technique and digital correction technique were employed.
在信号输入端设置了采样保持放大器（SHA），级电路中采用了低功耗运算跨导放大器（OTA）和动态比较器，并且使用了采样电容优化技术和数字校正技术。 - The display drive circuit of LCD projection system is divided into two kinds: sample-and-hold display driver and latch display driver.
液晶投影系统的显示驱动电路分为取样/保持式驱动电路和锁存式驱动电路两种，本文介绍了这两种类型的典型驱动电路并对它们进行了比较。 - A sample-and-hold amplifier ( SHA) was used to improve the signal-to-noise and distortion ratio ( SNDR) performance and the linearity of ADC.
在信号输入端采用了采样保持放大器（SHA）以提高信号-噪声失调比（SNDR）及ADC线性度。 - A Study on High Speed and High Precision Sample-and-Hold Amplifiers
新结构高速高精度采样保持放大器的研究 - The simulation results show that the sample-and-hold element can greatly reduce phase noise and spurious noise in the loop.
仿真结果表明，使用采样保持单元后可以显著降低环路中的相位噪声和杂散噪声。 - An IC electronic circuit is used to analogize the behavior of Josephson junction. A novel method based on a sample-and-hold circuit to generate the sin θ supercurrent is designed.
作者使用了由集成块所组成的电子线路来模拟Josephson结的性质，其特点是设计了一种新型的采样保存电路来模拟与sinθ成正比的超导电流。 - It is useful to solve the conflict between speed and DC gain of an amplifier in high-speed and high-resolution sample-and-hold circuit to use a speed compensation circuit.
采用速度补偿解决了高速高分辨采样保持电路对放大器要求增益高和速度快之间的矛盾。 - The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。 - This thesis directs another way, using the high-speed sub-picosecond, high-precision ADC and "Sample-and-hold" circuit, which are already mature products and technologies, to measure the clock parameters.
本文另辟蹊径，利用亚皮秒的高速、高精度的ADC采样-保持电路这一成熟的产品和技术来测量时钟参数。 - The front-end sample-and-hold circuit uses double-sample technique. Bootstrapped sampling switch is applied and achieves remarkable progress on the resolution and linearity of the system.
电路最前端的采样保持电路应用双采样技术，结合栅压自举采样开关，大幅提高了电路的精度和线性度。 - The optimization of sample-and-hold circuit relieves the high-speed sampling clock feedthrough and charge injection effect.
前端采样保持电路的优化有效缓解了高速采样下的时钟馈通和电荷注入效应，缓冲级巧妙地将衬底电容与输出隔开，提高了电路的线性度。